搜索资源列表
FIR
- 基于FPGA的FIR滤波器实现，含全部不源代码-FPGA-based FIR filter, including all non-source code
DSP-FIR-Filter
- 用DSP仿真实现FIR滤波器，整个工程文件齐全-DSP simulation of FIR filters, including the entire project file
FIR_filter
- FIR filter with weight function
Lab0603-fir
- 基于TMS320VC5509的的FIR滤波-Based on the FIR filter of the TMS320VC5509
FIR
- 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
FPGAFIR
- FPGA-based high-order FIR filter design
beta
- Fir verilog code implemented to find out the output of fir filter
FIR
- 基于MATLAB的FIR滤波器设计与滤波-MATLAB-based FIR filter design and filtering
FIRFilter
- 利用FIR 滤波器对图像进行采样，平滑。使用vc++ 6.0 和 opencv-using FIR filter to sample and smooth the image, based on VC++ 6.0 and openCV
vhdl
- FIR滤波器的性能参数 设计一个滤波器最基本的就是性能参数的,决定着滤波器的实际功能.比如阶数,截至频率。 本文滤波器设计参数 ①输入,输出数据宽度10位 ②阶数为4阶的线性相位FIR滤波器， ③类型:带通 -FIR filter performance parameters The design of a filter is the most basic performance parameters, determines the actual filter fu
Fir
- 基于TMS320F2812的FIR数字滤波器-FIR filter for F2812
fir
- This an examples of fir filter implemented in SystemC.-This is an examples of fir filter implemented in SystemC.
65jie
- 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点，但是要占用大量的资源。在多阶数的亚高频系统设计中，使用并行结构并不合算，但亚高频系统需要较高的处理速度，而串行架构往往达不到要求，因此，结合串并这两种设计方法的长处，在使用较少的硬件资源的同时实现了较高的处理速度，这里说明一种65阶八路并行、支路串行FIR滤波器的设计（实际使用了1个乘法器，8个乘累加器，一个累加器）。-String and FIR filter design: parallel FIR filter with a
fir
- c语言实现的FIR滤波器，用户输入FIR滤波器的参数。-c language of the FIR filter, FIR filter user input parameters.
fir
- 使用verilog语言实现的fir滤波器，使用了内部的触发器资源，优化。-Verilog language used to achieve the fir filter, the use of internal resources of the flip-flop, and optimize.
FIR
- 在TMS320VC5509中，FIR滤波器的信号滤波-In TMS320VC5509 in, FIR filter signal filtering
FIR
- This implementation of Low power Finite Impulse response filter design and implemented in Verilog-This is implementation of Low power Finite Impulse response filter design and implemented in Verilog
FIR_digital_filter_design
- FIR数字滤波器的设计:用窗函数法，频率采样法及优化设计法设计FIR滤波器的原理及方法,用MATLAB编程实现FIR数字滤波器的设计-FIR digital filter design: using window function method, frequency sampling method and optimal design of FIR filter design method principles and methods, using MATLAB programming desi
fir
- 利用VHDL语言，设计了一个11阶的FIR滤波器。简单易懂-The use of VHDL language, designed a 11-order FIR filter. Easy to understand. .
reload_fir
- 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload p